1. Field of the Invention
The present invention relates to a method and an apparatus for time-division multiplexing and demultiplexing of signals used in a digital transmission system, and more particularly to a method and an apparatus for time-division multiplexing and demultiplexing of signals, as well as a method and an apparatus for time-division demultiplexing of signals performed in a plurality of steps.
2. Description of the Related Art
In a digital transmission system, time-division multiplexing (TDM) technology has been widely used for transmitting a plurality of digital signals. For realizing the TDM system, it is indispensable to install a time-division multiplexer on a transmitter side, and a time-division demultiplexer on a receiver side. The time-division multiplexer multiplexes input digital signals, each having the same transmission rate. The time-division demultiplexer, on the other hand, demultiplexes the received multiplexed signal to restore the original digital signals.
FIG. 8 shows a conventionally used time-division multiplexing/demultiplexing apparatus. In this figure, the time-division multiplexing factor is assumed to be 16. A 16:1 time-division multiplexer 3 receives 15 digital input signals Si1 through Si15. One of the input signal, Si0, is inputted to the remaining input terminal 0 of the time-division multiplexer 3, after being inverted by an inverter 4. This inverted signal input is used as a frame synchronization signal, indicating the start position of each frame. The multiplexed signal Smpx is output on a transmission line 10.
On a receiver side, a 1:16 time-division demultiplexer 5 demultiplexes the time-division multiplexed signal Smpx supplied via a transmission line to produce 16 time-division demultiplexed signals So1-0 to So1-15 and outputs those signals.
A bit rotator circuit 7 rotates spatial orders of digital input signals So1-0 to So1-15 read from the 1:16 time-division demultiplexer 5, according to the applied clock signal CLK. Each time a clock pulse of the CLK is supplied from a frame synchronizing circuit 9 to be described later, the bit rotator circuit 7 rotates the order of the time-division separated signals So1-0 to So1-15, i.e., each input signal moves to the next adjacent output position. The permuted signals are outputted as output signals So1 through So15.
The frame synchronizing circuit 9 monitors the output from the bit rotator circuit 7 and transmits a control signal to the bit rotator circuit 7 to thereby synchronize frames of the 16:1 time-division multiplexer 3 and the 1:16 time-division demultiplexer 5. For monitoring the synchronization status, two outputs, So0 and So1, are supplied for the frame synchronizing circuit 9. Once the synchronization is established, signal So0 is always the inverted signal of So1 for every bit. On the other hand, when the synchronization is not established, So0 often coincides with So1. Therefore, synchronization can be monitored by detecting the coincidence frequency of So0 and So1. In order to detect this frequency, the frame synchronizing circuit 9 is typically composed of a well-known racing counter conducting both forward and backward protection. When the coincidence frequency increases, that is, frames for multiplexer/demultiplexer are not synchronized, pulse signal CLK is emitted from the frame synchronizing circuit, one pulse for each coincidence bit detected. After necessary permutation is performed in bit rotator circuit 7 according to the CLK input, and the coincidence frequency decrease follows, the pulses in the CLK vanishes. At this time, the synchronization is established.
However, the conventional time-division multiplexer/demultiplexer has the following problems:
When compared with an 8:1 or lower time-division multiplexing/demultiplexing apparatus for high speed digital signals of about 150 Mb/s, for example, 143 Mb/s for a broadcasting studio system and 155 Mb/s for an SDH system, a 16:1 or higher apparatus costs a few times more.
The reason is as follows: The circuit configurations of a time-division multiplexer and a time-division demultiplexer are comparatively simple for up to approximately 8:1. Even for several Gb/s, very high operation speed is not required for circuit components. For this multiplexity, there are commercially available multiplexer/demultiplexer ICs made on silicon substrate, available at a reasonable price. For multiplexers of around 16:1 or higher, however, circuit structure for the multiplexer/demultiplexer is significantly complicated. As timing margins decrease, high speed operation for each circuit component is critical, especially for bit rates of above several Gb/s. Although for this high speed operation, gallium arsenide ICs are available, they have a prohibitive price of several times that of comparable silicon ICs.
In view of the foregoing and other problems of the conventional apparatus, an object of the present invention is to provide an apparatus and method for time-division multiplexing/demultiplexing which can be operated at rates as high as several gigabits per second and can be fabricated with low cost.
In a first aspect of the present invention, an inventive apparatus for time-division multiplexing/demultiplexing of signals is provided which includes a first time-division multiplexer for multiplexing a plurality of input signals and a predetermined frame synchronization pattern signal to thereby generate first time-division multiplexed signals, a second time-division multiplexer for multiplexing each of the first time-division multiplexed signals to thereby generate a second time-division multiplexed signal, a first time-division demultiplexer for demultiplexing each of the second time-division multiplexed signals to thereby generate a predetermined number of first time-division demultiplexed signals, a second time-division demultiplexers for demultiplexing each of the first time-division demultiplexed signals to thereby generate second time-division demultiplexed signals, and a frame synchronizing circuit for protecting synchronization of signals by permuting orders of the second time-division demultiplexed signals until the same signal as the predetermined frame synchronization pattern signal is obtained from a second time-division demultiplexed signal corresponding to the predetermined frame synchronization pattern signal of the second time-division demultiplexed signals.
Additionally, the predetermined frame synchronization pattern signal used in the above apparatus may be an inverted signal of one of the plurality of input signals, and the frame synchronizing circuit permutes orders of the second time-division demultiplexed signals until one of the second time-division demultiplexed signals mismatches bit by bit with another one of the second time-division demultiplexed signals corresponding to the inverted signal.
Furthermore, the frame synchronizing circuit may preferably permute orders of the second time-division demultiplexed signals so that the phase differences among the second time-division demultiplexed signals are canceled.
Further, the above apparatus may include extra multiplexers and demultiplexers for performing up to n-th (where n is an integer) stage multiplexing/demultiplexing, in addition to the first and second time-division multiplexing processing and the first and second time-division demultiplexing processing.
Further, the numbers of the input signals and the first time-division multiplexed signals may be selected to number 15 and 8, respectively.
Further, the allowable order permutation patterns for the above selected numbers may preferably be as follows:
(a) from first signal of the second time-division demultiplexed signals to first terminal of the multiplexing/demultiplexing apparatus output terminals, from third to second, from fifth to third, from seventh to fourth, from ninth to fifth, from eleventh to sixth, from thirteenth to seventh, from fifteenth to eighth, from second to ninth, from fourth to tenth, from sixth to eleventh, from eighth to twelfth, from tenth to thirteenth, from twelfth to fourteenth, from fourteenth to fifteenth, from sixteenth to fifteenth; and
(b) k (k=1,2, . . . 15) positions rotation applied to the (a), with same direction for all the k""s.
Also, the following signals may preferably be delayed by one bit:
(1) for the (b) where k=1 and first signal moves to second terminal under the direction, the sixteenth signal;
(2) for the (b) where k=2 and first signal moves to second terminal under the direction, the fourteenth signal is added to the (1);
(3) for the (b) where k=3 and first signal moves to second terminal under the direction, the twelfth signal is added to the (2);
(4) for the (b) where k=4 and first signal moves to second terminal under the direction, the tenth signal is added to the (3);
(5) for the (b) where k=5 and first signal moves to second terminal under the direction, the eighth signal is added to the (4);
(6) for the (b) where k=6 and first signal moves to second terminal under the direction, the sixth signal is added to the (5);
(7) for the (b) where k=7 and first signal moves to second terminal under the direction, the fourth signal is added to the (6);
(8) for the (b) where k=8 and first signal moves to second terminal under the direction, the second signal is added to the (7);
(9) for the (b) where k=9 and first signal moves to second terminal under the direction, the fifteenth signal is added to the (8);
(10) for the (b) where k=10 and first signal moves to second terminal under the direction, the thirteenth signal is added to the (9);
(11) for the (b) where k=11 and first signal moves to second terminal under the direction, the eleventh signal is added to the (10);
(12) for the (b) where k=12 and first signal moves to second terminal under the direction, the ninth signal is added to the (11);
(13) for the (b) where k=13 and first signal moves to second terminal under the direction, the seventh signal is added to the (12);
(14) for the (b) where k=14 and first signal moves to second terminal under the direction, the fifth signal is added to the (13); and
(15) for the (b) where k=15 and first signal moves to second terminal under the direction, the third signal is added to the (14).